1. Field of the Invention
The present invention is directed to a semiconductor device, especially to a device comprising a dc voltage circuit for generating an internal supply voltage, a device comprising a memory cell array, and a device comprising a plurality of transistors having a SOI structure.
2. Background of the Invention
In order to perform various processes with only one semiconductor chip, there has been a semiconductor device comprising a semiconductor chip on which a plurality of devices are integrated and arranged. Since each of the devices may require a different supply voltage, it becomes necessary to generate an internal supply voltage which is different from an external supply voltage supplied from the outside.
FIG. 12 shows an example of the dc voltage circuit for generating one of the internal supply voltages inside the semiconductor chip. To nodes N1 and N3, different external supply voltages are applied, respectively. The external supply voltage applied to the node N3 includes a ground voltage. A transistor 3 connected to the node N1 supplies the internal supply voltage to an internal circuit 2 formed in a semiconductor chip 1. The output of the transistor 3 is controlled by a differential amplifier 4 so that the internal supply voltage corresponds to a reference voltage Vref. For that reason, in the dc voltage circuit comprised of the transistor 3 and the differential amplifier 4, the reference voltage Vref and the internal supply voltage are applied to an inverting input terminal and a non-inverting input terminal of the differential amplifier 4, respectively, and then the output of the differential amplifier 4 obtained by amplifying the difference in voltage between those terminals is transmitted to the gate of the transistor 3.
Further, for a large distance between the internal circuit 2 and a node N2 to which the internal supply voltage is applied from the dc voltage circuit, parasitic resistance between them causes a voltage drop, making the value of the internal supply voltage to be applied to the internal circuit 2 different from that of the reference voltage Vref. If the dc voltage circuit is formed in the vicinity of the internal circuit 2 to reduce the voltage drop, supply of the reference voltage Vref becomes difficult.
In order to improve processing efficiency, there has been a semiconductor device in which a logic and a memory are integrated on one semiconductor chip. In such a semiconductor device, an external bus would neither affect the processing nor limit the processing speed. A DRAM is one of the most frequently employed memories in such a semiconductor device. Though achieving high integration and low cost, the DRAM requires a boost voltage to be applied to a selected gate of a memory cell. A gate oxide film of a transistor in the memory cell, to which the boost voltage is applied, requires a certain degree of thickness.
FIG. 13 is a graph showing correlation among the external supply voltage supplied to the semiconductor chip from the outside, the boost voltage and the internal supply voltage both generated inside the semiconductor chip. In FIG. 13, the solid line with the reference numeral 31 indicates the internal supply voltage; the solid line with the reference numeral 32 indicates the boost voltage (VPP); the dotted line with the reference numeral 34 indicates a voltage two times the external supply voltage; and the dotted line with the reference numeral 35 indicates a voltage three times the external supply voltage. The internal supply voltage 31 has constantly been increased to obtain the boost voltage VPP.
As described above, in the semiconductor device comprising the conventional dc voltage circuit, the differential amplifier directly drives a gate voltage of the transistor for supplying the internal supply voltage. This increases an output load capacity of the differential amplifier and prevents a high-speed operation of the dc voltage circuit. Thus, when the internal circuit operates at high frequency, the internal supply voltage cannot be stable.
Further, parasitic resistance or the like prevents supply of the desired internal supply voltage to the internal circuit formed in any location in the semiconductor chip.
Moreover, besides the current necessary for charge or discharge of the boost voltage, another current is necessary to generate the boost voltage inside the semiconductor chip, which increases the consumption of current in the whole semiconductor chip.
A first aspect of the present invention is directed to a semiconductor device comprising: an internal circuit formed in a semiconductor chip connected to first and second power supplies, and inserted in a current path formed between first and second nodes to receive an internal supply voltage via the first node; a first insulated-gate transistor having a control electrode, a first current electrode connected to the first power supply, and a second current electrode connected to the first node; a second insulated-gate transistor having a first current electrode connected to the first current electrode of the first insulated-gate transistor, a control electrode and a second current electrode both connected to the control electrode of the first-insulated type gate transistor; a third insulated-gate transistor having a first current electrode connected to the second power supply, a second current electrode and a control electrode both connected to the second node; a fourth insulated-gate transistor having a control electrode connected to the control electrode of the third insulated-gate transistor, a first current electrode connected to the second power supply, and a second current electrode connected to the second current electrode of the second insulated-gate transistor; and a voltage supply circuit for supplying an internal supply voltage to the first node.
Preferably, according to a second aspect of the present invention, a current flowing through the first and third insulated-gate transistors is greater than that flowing through the second and fourth insulated-gate transistors.
A third aspect of the present invention is directed to a semiconductor device comprising: an internal circuit formed in a semiconductor chip connected to first and second power supplies to receive an internal supply voltage; a first insulated-gate transistor having a control electrode, a second current electrode connected to a node for supplying the internal supply voltage to the internal circuit, and a first current electrode connected to the first power supply; a second insulated-gate transistor having a control electrode connected to the control electrode of the first insulated-gate transistor, a first current electrode connected to the first current electrode of the first insulated-gate transistor, and a second current electrode connected to the control electrode of the first insulated-gate transistor; a third insulated-gate transistor having a control electrode, a first current electrode connected to the second power supply and a second current electrode connected to the second current electrode of the second insulated-gate transistor; and a differential amplifier having an output terminal connected to the control electrode of the third insulated-gate transistor, a non-inverting input terminal connected to the node, and an inverting input terminal to which a reference voltage is applied, wherein a current flowing through the first insulated-gate transistor is greater than that flowing through the second insulated-gate transistor.
Preferably, according to a fourth aspect of the present invention, the semiconductor device further comprises a fourth insulated-gate transistor connected in series between the second power supply and the second current electrode of the third insulated-gate transistor, the fourth insulated gate transistor having a control electrode connected to the output terminal of the differential amplifier.
A fifth aspect of the present invention is directed to a semiconductor device comprising: an internal circuit formed in a semiconductor chip connected to first and second power supplies, the internal circuit receiving a first voltage; a boost circuit capable of generating a second voltage, higher than the first voltage, from the first and second power supplies at a first node connected to the internal circuit; a differential amplifier having a first terminal to which a voltage, obtained by subtracting a predetermined potential difference from a voltage at the first node, is applied, a second terminal to which a reference voltage is applied, and an output terminal for amplifying a potential difference between the first and second terminals; a current control means connected to the output terminal of the differential amplifier as well as connected between the first power supply and the first node, the current control means controlling a current flowing from the first power supply to the first node in accordance with a voltage at the output terminal of the differential amplifier; a current source connected between the first node and the second power supply, the current source supplying a current between the first node and the second power supply; and a control means for turning off the boost circuit when a voltage outputted from the first power supply is higher than the second voltage.
A sixth aspect of the present invention is directed to a semiconductor device comprising: a memory cell array having a plurality of blocks and a plurality of word lines comprised of a plurality of portions divided for each of the plurality of blocks to select memory cells of the plurality of blocks; a row decoder for selecting a row to select the word line; a word line driver provided for each of the plurality of blocks to supply a predetermined voltage to the portion; and a transfer gate provided between each of the plurality of portions to connect the plurality of portions, wherein data is read from or written to a row selected by the row decoder by transferring a charge between the plurality of portions adjacent to each other, in accordance with continuity or non-continuity of the transfer gate for the plurality of blocks in the memory cell array.
A seventh aspect of the present invention is directed to a semiconductor device having an epitaxial layer formed on an insulator. The semiconductor device comprises: a plurality of transistors having an electrode region ranging from the epitaxial layer to the insulator, wherein the electrode regions of transistors, having different conductivity types and adjacent to each other, are formed close to each other, the transistors being included in the plurality of transistors.
In accordance with the semiconductor device of the first aspect, since the internal circuit receives almost the same amount of current with its consuming current from the first and third insulated-gate transistors, supply of current from the voltage supply circuit is almost unnecessary, reducing an error of the supplied voltage. Besides, supply of the reference voltage to the first through fourth insulated-gate transistors is unnecessary, so that the internal circuit for receiving the current from the first through fourth insulated-gate transistors has a wider freedom of location.
In accordance with the semiconductor device of the second aspect, current consumption can be reduced except in the internal circuit.
In accordance with the semiconductor device of the third aspect, the third transistor of a smaller size can reduce a load for driving the differential amplifier. Thus, even if the internal circuit operates at high frequency, the semiconductor device can be performed at high speed by suppressing fluctuation in voltage at the node.
In accordance with the semiconductor device of the fourth aspect, when the differential amplifier turns off the third insulated-gate transistor, the fourth insulated-gate transistor improves an operating certainty of the semiconductor device.
In accordance with the semiconductor device of the fifth aspect, when the second voltage is lower than the voltage supplied from the first power supply, the boost circuit is stopped, and the voltage at the first power supply is dropped to be used as the boost voltage. This reduces current consumption by the voltage increase.
In accordance with the semiconductor device of the sixth aspect, since charge is sequentially transferred to each divided portion of the word line, part of the charge can be used repeatedly for the plurality of portions, reducing power consumption by the word line.
In accordance with the semiconductor device of the seventh aspect, it is possible to omit the wire connecting the electrode regions of the transistors having different conductivity types and adjacent to each other. Thus, power consumption can be reduced by reducing the load capacity.
The object of the present invention is to obtain the stable internal supply voltage by increasing the operating speed of the dc voltage circuit with reduction in the load capacity for driving the differential amplifier, and further to reduce the consumption of current in the dc voltage circuit. The consumption of current in the semiconductor chip can also be reduced by switching a boost voltage generating means in accordance with the external supply voltage or by effectively using a charge in the semiconductor device. Further, the SOI structure reduces a wiring capacity of the semiconductor device, and reduces power consumption.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.